The 32nd Edition seminar of DSDSD will feature talks by
Marcel Weisgut (HPI)
Nils Strassenburg (HPI)
Evaluating CXL Memory Performance
The Compute Express Link (CXL) standard enables new forms of memory management and access across devices and servers. Based on PCIe, it enables cache coherent access to remote memory. This widens the design space for database systems by expanding the available memory beyond memory local to the CPU. Efficiently utilizing CXL-attached memory requires conscious decisions of data systems about data placement and management. In this work, we provide an in-depth analysis of database operation performance with data interleaved across multiple CXL memory devices. We evaluate memory access performance for basic access patterns and the performance impact of placing data across multiple CXL memory devices for in-memory column scans and in-memory B+tree operations.
Marcel Weisgut is a PhD student at the Hasso Plattner Institute, specializing in data management utilizing modern hardware in the Data Engineering Systems group led by Tilmann Rabl. He received his master’s degree from HPI in 2021, focusing on in-memory data management in Hasso Plattner’s research group. During his master’s studies, he contributed to the columnar open-source in-memory database system Hyrise and interned with the SAP HANA development team at SAP Labs Korea. His current research focuses on utilizing memory attached to a CPU via the cache-coherent interconnect Compute Express Link (CXL) for database systems.